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1

Jitter transfer characteristics of delay-locked loops - theories and design techniques

Lee, M.-J.E., Dally, W.J., Greer, T., Hiok-Tiaq Ng, Farjad-Rad, R., Poulton, J., Senthinathan, R.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2003

Language:

english

File:

PDF, 583 KB

english, 2003

2

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

Farjad-Rad, R., Dally, W., Hiok-Tiaq Ng, Senthinathan, R., Lee, M.-J.E., Rathi, R., Poulton, J.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2002

Language:

english

File:

PDF, 1.25 MB

english, 2002

3

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

Farjad-Rad, R., Nguyen, A., Tran, J.M., Greer, T., Poulton, J., Dally, W.J., Edmondson, J.H., Senthinathan, R., Rathi, R., Lee, M.-J.E., Hiok-Tiaq Ng

Journal:

IEEE Journal of Solid-State Circuits

Year:

2004

Language:

english

File:

PDF, 1.46 MB

english, 2004

4

[IEEE CICC Custom Integrated Circuits Conference - San Jose, CA, USA (21-24 Sept. 2003)] Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003. - A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

Hiok-Tiaq Ng,, Lee, M.-J.E., Farjad-Rad, R., Senthinathan, R., Dally, W.J., Nguyen, A., Rathi, R., Greer, T., Poulton, J., Edmondson, J., Tran, J.

Year:

2003

Language:

english

File:

PDF, 374 KB

english, 2003

5

[IEEE 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA, USA (2007.02.11-2007.02.15)] 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR

Leibowitz, Brian S., Kizer, Jade, Lee, Haechang, Chen, Fred, Ho, Andrew, Jeeradit, Metha, Bansal, Akash, Greer, Trey, Li, Simon, Farjad-Rad, Ramin, Stonecypher, William, Frans, Yohan, Daly, Barry, Hea

Year:

2007

Language:

english

File:

PDF, 2.82 MB

english, 2007

6

[IEEE 2015 IEEE Hot Chips 27 Symposium (HCS) - Cupertino, CA, USA (2015.8.22-2015.8.25)] 2015 IEEE Hot Chips 27 Symposium (HCS) - 10G | 5G | 2.5G | 1G | 100M physical layer PHY: HOT CHIPS 2015 conference

Shirani, Ramin, Farjad-Rad, Ramin

Year:

2015

Language:

english

File:

PDF, 3.60 MB

english, 2015

7

A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling

Chih-Kong Ken Yang, Ramin Farjad-Rad, Horowitz, M.A.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1998

Language:

english

File:

PDF, 253 KB

english, 1998

8

[IEEE 1993 Symposium on VLSI Circuits - Kyoto, Japan (1997.06.14-1997.06.14)] Symposium on VLSI Circuits - A 0.6/spl mu/m CMOS 4Gb/s Transceiver With Data Recovery Using Oversampling

Chih-Kong Ken Yang,, Farjad-Rad,, Horowitz,

Year:

1997

Language:

english

File:

PDF, 295 KB

english, 1997

9

A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

Farjad-Rad, R., Yang, C.-K.K., Horowitz, M.A., Lee, T.H.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1999

Language:

english

File:

PDF, 322 KB

english, 1999

10

A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver

Farjad-Rad, R., Yang, C.-K.K., Horowitz, M.A.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2000

Language:

english

File:

PDF, 377 KB

english, 2000

11

A second-order semidigital clock recovery circuit based on injection locking

Hiok-Tiaq Ng, Farjad-Rad, R., Lee, M.-J.E., Dally, W.J., Greer, T., Poulton, J., Edmondson, J.H., Rathi, R., Senthinathan, R.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2003

Language:

english

File:

PDF, 898 KB

english, 2003

12

[Japan Soc. Appl. Phys 1999 Symposium on VLSI Circuits. Digest of Technical Papers - Kyoto, Japan (17-19 June 1999)] 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) - A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver

Farjad-Rad, R., Chih-Kong Ken Yang,, Horowitz, M., Lee, T.

Year:

1999

Language:

english

File:

PDF, 516 KB

english, 1999

13

[IEEE 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) - San Francisco, CA, USA (Feb 3-7, 2002)] 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) - A 0.2-2GHz 12mW multiplying DLL for low-jitter clock synthesis in highly-integrated data-communication chips

Farjad-rad, R., Dally, W., Mg, H., Poulton, J., Stone, T., Rathi, R., Lee, E., Huang, D., Nathan, R.

Year:

2002

Language:

english

File:

PDF, 607 KB

english, 2002

14

[IEEE Comput. Soc 21st International Conference on Computer Design - San Jose, CA, USA (13-15 Oct. 2003)] Proceedings 21st International Conference on Computer Design - CMOS high-speed I/Os - present and future

Lee, M.-J.E., Dally, W.J., Farjad-Rad, R., Ng, H.-T., Ramesh Senthinathan,, Edmondson, J., Poulton, J.

Year:

2003

Language:

english

File:

PDF, 400 KB

english, 2003

15

[Japan Soc. Appl. Phys 2003 Symposium on VLSI Circuits. Digest of Technical Papers - Kyoto, Japan (12-14 June 2003)] 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) - 0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization

Farjad-Rad, R., Hiok-Taiq Ng,, Edward Lee, M.-J., Senthinathan, R., Dally, W.J., Nguyen, A., Rathi, R., Poulton, J., Edmondson, J., Tran, J., Yazdanmehr, H.

Year:

2003

Language:

english

File:

PDF, 432 KB

english, 2003

16

[IEEE IEEE International Solid-State Circuits Conference - San Francisco, CA, USA (9-13 Feb. 2003)] 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. - A second-order semi-digital clock recovery circuit based on injection locking

Lee, M.-J.E., Dally, W.J., Poulton, J., Greer, T., Edmondson, J., Farjad-Rad, R., Hiok-Tiaq Ng,, Rathi, R., Senthinathan, R.

Year:

2003

Language:

english

File:

PDF, 430 KB

english, 2003

17

[IEEE 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA, USA (3-7 Feb. 2002)] 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) - A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips

Farjad-Rad, R., Dally, W., Hoik-Tiaq Ng,, Poulton, J., Stone, T., Rathi, R., Lee, E., Huang, D., Nathan, R.

Year:

2002

Language:

english

File:

PDF, 1.66 MB

english, 2002